Conversion of binary data into a continuous physical signal finds application in virtually any domain of digital information processing technology.
Schematically represented in Part A of FIG. 1 is an example of a sequence of data bits 12. The sequence 12 comprises a total of seven data bits, each of which may assume either a logical “zero” (“0”) state or a logical “one” (“1”) state. A first bit 11 and a subsequent second bit 13 in the exemplary sequence 12 are in the states “0” and “1”, respectively. In the example shown, the seven data bits of the sequence define the sequence “0 1 0 1 1 0 0”. In practice, a sequence of data bits may comprise millions or billions of data bits. The sequence of data bits 12 may be communicated from one device to another device by transmitting it in the form of a binary signal 14 (Part B of the figure). The binary signal 14 is the time-dependence of a physical quantity, typically a frequency or amplitude of an electrical voltage or current, or of an electromagnetic field at a given spatial position. The signal value, defined as the instantaneous value of the physical quantity, varies in time t in accordance with the sequence of data bits 12. In a Frequency Shift Keying (FSK) system, the signal value is typically the oscillation frequency of a voltage or current, to be transmitted via transmission lines or to be fed to an antenna. Each data bit in the sequence 12 is allocated a time slot of length T during which the signal value assumes either a first signal value F0 or second signal value F1, depending on whether the respective data bit is the “one” or “zero” state. The inverse of the length T is the bit rate, that is, the number of data bits transmitted per time. It is noted that the signal 14 thus defined varies abruptly whenever a data bit and the subsequent data bit (e.g. bit 11 and bit 13) differ. As is well known, an abrupt change in value of a function corresponds to a wide Fourier spectrum of that function. Thus, for applications in which a narrow bandwidth of the binary signal is desired, the binary data is encoded in the form of a signal 16 varying more gently, as is illustrated in Part C of the Figure. In the domain of FSK systems, the desire of reducing the bandwidth of the transmitted signal has led to the development of Gaussian Frequency Shift Keying (GFSK). According to this method, a wideband signal such as the binary signal 14 is passed through a Gaussian filter in order to generate a signal (in the example, the signal 16) having a reduced bandwidth. The signal having the reduced bandwidth is essentially the convolution of the wideband signal 14 and a Gauss function. The Gaussian filter may be an analog filter, or it may be implemented digitally, involving either a sampling of the wideband input signal 14 or direct generation from the sequence of data bits 12.
FIG. 2 schematically shows a signal shaper 10. The signal shaper 10 has an input port for receiving a sequence of data bits 12 and an output port for delivering a signal 16 in which the sequence of data bits 12 is encoded. The signal 16 is a physical quantity that varies in time as prescribed by the sequence of data bits 12. In the case where the data bits of the sequence 12 are fed successively to the signal shaper, i.e. in the form of a bit stream having a bit rate, the bit rate of the emitted signal 16 may be equal to or greater than the rate of the received bit stream. A signal shaper of this type finds application in a vast variety of digital signal processing devices. The signal shaper 10 may, for example, be part of an FSK system, in particular for applications in which a narrow bandwidth of the emitted signal is required, e.g. in telecommunications. The signal shaper 10 may in particular be employed in automotive applications, such as tire pressure monitoring systems (TPMS) or remote keyless entry (RKE) systems.
Shown in FIG. 3 is an example of an embodiment of a signal shaper 10 according to the prior art, for use within a frequency shift keying system. The signal shaper 10 comprises a Gaussian filter 24 for receiving a time-dependent binary voltage 20 representing binary data, and an analog phase-locked loop (PLL) 26. The PLL 26 comprises, as a core element, a voltage-controlled oscillator (VCO) 28 generating a frequency F in the radio-frequency range (i.e. a few Hertz up to many Gigahertz). The output signal 16 of the VCO, that is, a voltage oscillating at the frequency F, is coupled via a frequency divider 30 to a phase comparator 32 controlling an input voltage of the VCO 28, so as to provide a negative feedback signal to the VCO 28, thereby stabilizing the oscillation frequency F of the VCO. The phase comparator 32 receives as input a fixed reference frequency Fref. The reference frequency Fref being lower than the generated frequency F, it serves to set a reference phase to which the phase of the VCO is continually adapted. Coupled between the phase comparator 18 and the summator 36 is a low-pass filter 34 (loop filter) for stabilizing the loop. Further coupled between the loop filter 34 and the VCO 28 is a summator 36 for adding to the control voltage output by the loop filter 34 an external voltage 22. The frequency F generated by the PLL 26 can thus be modulated externally (that is, from outside the loop) by varying the external control voltage 22. The external voltage 22 is the output generated by the Gaussian filter 24, i.e. a binary signal having a reduced band-width. Thus the frequency F output by the VCO 28 is modulated with the variation of the external voltage 22, which in turn represents the data encoded in the binary signal 20.
The approach described above with reference to FIG. 3 is analog in the sense that the output frequency of the PLL 26 is modulated by a continuous analog signal, namely the voltage 22 received from the Gaussian filter 24. This approach has been realized for years, but is not necessarily suitable for integrated solutions as the gain of the VCO 28 is usually not well controlled.